In the sub-nanometer generation of fabrication process of a semiconductor device, one demand is to shrink a line width of the semiconductor device and to obviate a short channel effect therein, and another demand is to increase a response speed and to reduce power consumption thereof. In order to meet the above demands, a semiconductor device having a broader channel width such as a FIN field effect transistor (FINFET) is a solution. However, in the case of obtaining a functional circuit that needs to fabricate at least one of plural nanometer-scale semiconductor devices formed in a substrate having a differentiated spatial channel width from others, one aspect is to overcome a resolution limitation of conventional lithography processes, and another aspect is to maintain a pattern integrity of the spatial channels of the plural nanometer-scale semiconductor devices.
Therefore, there is a need of providing an improved method of fabricating nanometer-scale spatial semiconductor devices having differentiated line widths.